1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device applicable to a high data rate memory with easy.
2. Background of the Related Art
As a system operation frequency of the semiconductor memory device becomes the higher, a performance of the semiconductor memory device becomes the higher, too. However, DRAMs (Dynamic Random Access Memories) which occupy most of main memories still have a significant difference in view of performance from CPUs (Central Processing Unit), to overcome which a DRAM in which a data band width can be improved under the same operation frequency is under development. In general, being a reference for determining a performance of a memory, the data band width represents an amount of data the memory can access for one second. For example, for a memory operative synchronous to a system operation frequency of 100 MHZ, the data band width per pin of the memory is 100 Mbps (Mbits/sec). The data band width can be improved, simply by increasing the system operation frequency, or either by operating an internal operating frequency two times or four times of the system operating frequency while keeping the system operating frequency the same, with data reading or writing at a rising edge of the operating frequency or by synchronizing the data to a rising and a falling edges of a system clock. In the latter method, the data band width per pin of memory can be 200 Mbps or 400 Mbps. Alike a general SDRAM, a DDR SDRAM (Double Data Rate Synchronous DRAM) has a number of CAS latency modes (CL) (Column Address Select Signal Latency Mode). For example, in CL2, data is available after two system clock cycles from a read command, in CL2.5, data is available after 2.5 system clock cycles, and in CL3, after 3 system clock cycles. There are such different CL modes, for allowing a user to use the SDRAM in different frequencies by allowing the user to determine a CL mode such that, because a time required for a read command in an SDRAM, i.e., a time period tAA required from a column address latch to a first data output is nothing to do with the frequency, the tAA is allowed regardless of the system operation frequency. Therefore, a latency control circuit is required for operating at a fixed CL according to an employed operating frequency.
Referring to FIG. 1, a related art SDR (Single Data Rate) SDRAM, disclosed in U.S. Pat. No. 5,655,105, is provided with a memory array 101, a controlling unit 102, a data bus 105, an address bus 106, an I/O (input output) interface 110, an address register 112 for receiving a row or a column address through the address bus 106 and clocking the received address, a row address path 114 for providing the row address to the memory array 101, a column address path 116 for providing the column address to the memory array 101, an input data path 240 for providing a data from the data bus 105 to the I/O interface 110, an output data path 242 for providing a data from the I/O interface 110 to the data bus 105, and a mask register. The controlling unit 102 has a system clock signal CLK, a clock enable signal CKE, a mode register 150 for generating a latency mode, a command decoder, a latency controller 136. There are a plurality of command signals provided to the command decoder, including a chip selection signal CSB for controlling read/write on the SDRAM, a write enable signal WEB, a column address selection signal CASB, a row address selection signal RASB, and a block write selection signal DSF. The row address path 114 is provided with a row address multiplexer 118 for receiving a row address from the address register 112, a refresh unit 120 for providing a refresh signal to the row address multiplexer 118 to support maintaining an enable of a row, a row latch 122 for receiving an output from the row address multiplexer 118, and a row decoder 124 for receiving an output from the row latch 122 and connected to the memory array 101 to have one 8 bit address. The column address path 116 is provided with a column address latch 128 for receiving a column address from the address register 112 and holding the column address, a burst counter 130 for receiving an output from the column address latch 128, a column address buffer 132 for being driven by the burst counter 130, and a column decoder 134 for storage of 8 bit column addresses of the column address buffer 132 and enabled memory array 101. And, the I/O interface 110 is enabled by a column address on the same with the column decoder 134, the burst counter 130 passes the column address without any change when the multiple latency SDRAM is not in a block write mode, passes the address immediately in a latency 2 operation, and passes a delayed address in a latency 3 operation. The input data path 240 is provided with a master data input register 246 for receiving a data from the data bus 105 and clocking the data by a DINL, a data-in latch command, a first, and a second slaves 250 and 252 for receiving an output from the master data input register 246 and clocking the same by a master-slave write path signal M-S WRITEPASS from the latency controlling unit 136, and a color 254 for receiving an output from the master data input register 246, and a multiplexer 266 for receiving outputs from the first, and second slaves 250 and 252 and the color 254. And, the output data path 242 has a master input register, a by-pass, and a data output register.
However, the related semiconductor memory device of SDR SDRAM has the following problems.
First, the latency modes of 2 or 3 can not support a DDR SDRAM latency mode like latency 2.5 in which read/write is synchronized to both side edges of the system clock, i.e., a data read is carried out in a half cycle of the system clock.
Second, because the frequency is fixed to an optimal frequency, the circuit should be modified every time an employed frequency is changed for providing an additional control signal for operating a desired latency mode even if the frequency has changed.